1. Field of the Invention
The present invention relates to a capacitor in which a plurality of inner electrodes are alternately layered so as to face each other sandwiching dielectric layers and, more particularly, to a multilayer capacitor including a via electrode for passing current from a terminal electrode to the inner electrodes, and a method for manufacturing the capacitor.
2. Description of the Related Art
In a multilayer capacitor, an inner electrode is structured by a first electrode layer and a second electrode layer sandwiching dielectric layers, and a plurality of via electrodes are provided along the layer stacking direction to pass current among these electrode layers. See, for example, Patent Documents 1 and 2 below. The multilayer capacitor can be used as a decoupling capacitor, for example, to reduce the power noise of ICs.
[Patent Document 1] JP-A-2002-359141
[Patent Document 2] JP-A-2003-158030
For such applications, the capacitor requires a large capacitance and a low inductance-, and to achieve this, the inner electrodes have generally been multilayered and connected with columnar via electrodes formed penetrating in a direction normal to the planes of dielectric layers inside the capacitor so as to reduce inductance of the capacitor. On the dielectric layers there are portions where electrodes are formed and portions where electrodes are not formed. Therefore, when multiple layers of electrodes are formed in the dielectric layer, in the resulting capacitor the part where electrodes are formed and the part where no electrodes are formed have different thicknesses, thereby forming a step (electrode step) or rather causing an electrode height difference. To eliminate such an electrode step, the capacitor generally has on its surface layer a thick dielectric layer portion called a base layer that absorbs the electrode height difference.